Arizona ERA Sonoran Technology Show Seminars

Technical Seminars

REGISTER ONLINE

REGISTRATION DEADLINE EXTENDED TO DEC. 5!

Hilton Phoenix Chandler – 2929 W. Frye Rd., Chandler, AZ 85224
Dec. 6, 2018

TIME: Seminars are being held at 9 – 11:30 a.m. and 12 – 2 p.m.
FEE: There is no cost to attend, continental breakfast or lunch is included.
Register by Dec. 5. Seating is limited.

Immediately following the seminars, please join us at the ERA Arizona Chapter Sonoran Technology Show, scheduled from 2 – 8 p.m., featuring a gathering of hundreds of technical suppliers!

Questions? Contact Heather Mueller at hmueller@englishsales.com, or by phone at 480-203-6579.

Click seminar name to view details. Click again to close.


9 AM – Dialog Semiconductor Presents GreenPak™ Programmable Mixed-Signal Matrix – Sponsored by Dialog Semiconductor and ETS Southwest

TIME: 9 – 11:30 a.m. Includes continental breakfast.
MEETING ROOM: Maricopa Room 2

GoConfigure! is a cost effective NVM programmable device that enables innovators to integrate many system functions while minimizing component count, board space, and power consumption. Using Dialog’s GreenPAK Designer Software and GreenPAK Development Kit, designers can create and program a custom circuit in minutes.

GreenPAK Is Ideal For:

• Functional replacement of popular mixed-signal standard products, often in combination.
• Providing reliable hardware safety and reset functions for software coded devices, such as SoCs and microcontrollers.
• Overcoming last minute design challenges/issues.

Benefits Over Discrete Design

Smaller PCB footprint – Plastic packages as small as 1.0 x 1.2 mm.
Fewer Components/Lower Cost – A typical GreenPAK implementation removes from 10 to 30 components per instance.
Higher Reliability – Fewer PCB interconnects increases reliability.
Faster Design – Develop and program devices in minutes at your desk. Quickly respond to changing design requirements and increase productivity at the design and prototype verification stages.
Lower Power – Save power by removing discrete resistors in voltage dividers, pull ups, pull downs, etc., and replacing with low-power, integrated components. Further reduce power consumption using the sleep function.
• Design Security – Makes reverse engineering substantially more difficult by disabling the read-back of NVM configuration, obscuring design details.
• Tested Solutions – Every GreenPAK IC is tested, while a discrete circuit is not tested prior to the final board level test.

REGISTER ONLINE

9 AM – Thom Luke Sales, Arizona Hosts ST Micro Seminar

TIME: 9 – 11:30 a.m. Includes continental breakfast
MEETING ROOM: Maricopa Room 1

ST Analog & Power Rad-Hard Portfolio, New Product Updates, 28nm FDSOI Space Capabilities
.

Space Products

Electronics in space applications are subjected to high levels of radiation from high-energy particles (heavy ions). ST offers a large portfolio of products specifically designed, packaged, tested and qualified so they comply with the standards for aerospace defined by the qualifying agency. ST has supported European aerospace applications since 1977, being the first company qualified by the ESA (European Space Agency) since the agency’s inception. ST has broadened its efforts by qualifying products according to the American QML-V RHA (Radiation Hardness Assurance) and JAN S standards (of the U.S. DLA – Defense Logistics Agency). Today, ST is proud to be the sole company worldwide qualified for both American and European standards.

ST has a broad product portfolio from which products can be drawn for aerospace and defense applications. Among these are products with extended temperatures ranges and radiation hardended devices.

● Diodes and rectifiers
● BiPolar, Power MOSFET and IGBTs
● Power and Smart Power ICs
● Logic ICs and Comparators
● A/D converteros and Op Amps
● 32-bit microcontrollers
● Audio and positioning
● RF ICs
● Motor drivers

REGISTER ONLINE

12 PM – Arrow Electronics Hosts Microchip Technology Seminar

TIME: 12 – 2 p.m. Includes lunch
MEETING ROOM: Maricopa Room 2

Microchip Technology Inc. is a leading provider of microcontroller, analog, FPGA, connectivity and power management semiconductors. Its easy-to-use development tools and comprehensive product portfolio enable customers to create optimal designs which reduce risk while lowering total system cost and time to market. The company’s solutions serve more than 130,000 customers across the industrial, automotive, consumer, aerospace and defense, communications and computing markets. Headquartered in Chandler, Ariz., Microchip offers outstanding technical support along with dependable delivery and quality.

Subjects covered:

● What is a cloud gateway?
● Why use a cloud gateway?
● What’s the difference between Alexa/Google home automation a cloud gateway?
● What markets are adopting cloud data acquisition and local processing
● See a cloud gateway in action
● How to create a cloud gateway and AWS nodes with MCHP MPU’s and CPU’s
● What’s new with MPU?

REGISTER ONLINE

12 PM – Vicor Sponsors Modular Solutions for Your Power System

TIME: 12 – 2 p.m. Includes lunch
MEETING ROOM: Yavapai Room

Scope of Seminar: Modular power components and complete power systems based upon a portfolio of patented technologies. Attend this seminar to learn the latest innovations of Vicor’s solutions with a focus on Factorized Power and battery charging.

Overview of Seminar

As electronic systems continue to trend toward lower voltages with higher currents and as the speed of contemporary loads, such as state-of-the-art processors and memory, continues to increase, the power systems designer is challenged to provide small, cost-effective and efficient solutions that offer the requisite performance. Traditional power architectures cannot, in the long run, provide the required performance. Vicor’s new Factorized Power Architecture™ (FPA) and its new families of integrated power components, called VI Chips, provides a revolutionary new and optimal power conversion solution that addresses the challenge in every respect.

REGISTER ONLINE

12 PM – Lattice Semiconductor Ultra-Low Power Lattice sensAI

TIME: 12 – 2 p.m. Includes lunch
MEETING ROOM: Maricopa Room 2

Over recent decades, system design has evolved from one processing topology to another, from centralized to distributed architectures and back again in a constant search for the ideal solution. As computational requirements have skyrocketed, the industry has migrated to a more centralized approach built around cloud-based computing. Today businesses prefer to perform high-level computation and analysis in the cloud where they can take advantage of its virtually unlimited computational and storage resources, high reliability and low cost.

As companies adopt machine learning techniques and employ higher levels of artificial intelligence (AI), it seems likely the computational resources in the cloud will play an increasingly pivotal role in most organizations plans. But the cloud is not the ideal solution for all applications. Today’s focus on machine learning for AI typically occurs in two phases. First, systems are trained to learn a new capability by collecting and analyzing large amounts of existing data. For example, a system learns how to recognize a gesture by viewing thousands of images. This phase can be highly compute-intensive. Neural networks in machine learning for applications such as image recognition can require Terabytes of data and exaflops of computational power. Accordingly, these tasks are typically performed in the data center.

REGISTER ONLINE

Powered by WishList Member - Membership Software